The successful application of the high k/metal gate route in technology nodes of 45 nm makes it a key modular engineering, which is essential for technology nodes below 30 nm. Nowadays, only the Intel Corporation, which persisted in gate last route succeeding in the mass-production at the 45 nm and 32 nm technology nodes. In recent years, the industry giants like Samsung, TMSC, Infineon etc, which follow closely the IBM industrial alliance, also change their R&D focus from gate first to the gate last route.
For gate last route, it is believed in the industry that chemical mechanical planarization (CMP) process development is one of the most challenging. In gate last route, two CMP processes are required in the first generation of high k/metal gate technology, namely, the poly-open planarization CMP (POP CMP) for opening the top of the polycrystalline gate and the Al metal gate CMP. In the second generation of high k/metal gate technology, in addition to the above two CMP processes, a W—Al buffer layer CMP process is further required, and an ideal schematic view for the structure after planarization is shown in FIG. 1. According to the CMP process, after an Al gate 10 is formed by the metal gate CMP, contact holes are etched through over the source/drain regions, metal tungsten (W) is filled in the contact holes by CVD process, and the surplus W is removed by CMP process to form W plugs 11. This W—Al buffer CMP process poses several big challenges for the CMP technique, for example, the removal rate selectivity among the metal W, Al, and the oxide, the electrochemical corrosion between W and Al, and the Al metal gate recess and W plug after CMP process.
Below 45 nm technology node, the conventional CMP faces one great challenge is that how to improve the within die uniformity. The within die uniformity is a critical planarization characteristic for CMP process. After finishing contact holes etch and contact silicide, barrier layer Ti/TiN and metal W is respectively deposited in the contact holes by PVD and CVD process. The W depth of the contact holes is usually in the range of 1000-1500 Å. After deposition of W layer 12, the step height h between the top of contact hole area and non-contact hole area may be 1000-3000 Å or even larger due to very large device density, as shown in FIG. 2. If using conventional W CMP process, the step height will be transferred to the end of CMP process, so the recess 13 appear on top of W plugs, as shown in FIG. 3. The W plugs recess is significantly adverse for next step of connecting Cu lines, which may even result in a contact open between W plugs and Cu lines. In order to solve this problem, a step of oxide CMP buffer is needed to remove some oxide after finishing conventional W CMP, so that W plugs will protrude to some extent. As can be seen in FIG. 1, in the second generation of high k/metal gate technology, W plug structure differs from the process structure before 45 nm, and the relatively thin oxide separating layer results in a very small adjusting window for the oxide buffer CMP process. In addition, although W plug may protrude by means of the oxide buffer CMP, the Al metal gate electrodes will also protrude, so that leakage current between metal gates or between metal gates and W plugs may be greatly increased, which degrades electrical properties of the device, and even results a low yield.
Therefore, an efficient metal plug CMP is necessary for the second generation of high k/metal gate technology in the gate last route, which can meet the requirements of within die uniformity and device electrical performances.